ICon Semiconductor offers fully-customized ADC and DAC IPs up to 10Gsps tailored for highly integrated System-on-Chip designs. License options from 40nm to FinFET nodes supporting all mainstream foundries.

 

Our design team has extensive experience in delivering fully integrated IP solutions for a diverse customer base (including satellite communications, 5G base stations, instrumentation applications), offering custom products and services that exceed performance requirements to fulfill any applications needs.
 

IP Deliverables

• Design Report: Comprehensive design review including extracted simulation results for key parameters across process, voltage, and temperature. Monte-Carlo simulation results where necessary.

• Verification Report: LVS and DRC logs with tool version numbers.

• Functional Model: SystemVerilog functional model for system simulation and SoC integration.

• Tapeout Checklist: Checklist outlining key parameters to verify before tapeout.

• Constraints: Timing constraints for the digital interface.

• Integration Guide: Detailed instructions for top-level integration, test requirements, and post-silicon characterization.

• LEF: Pin-exact LEF model for floorplanning purposes, providing an area estimate for the design and aiding top-level SoC floorplanning. level.

• CDL: Complete transistor-level netlist for the IP, uniquified to prevent name clashes with standard cells or common blocks at the SoC level. This file is for confirming LVS results at SoC level.

• GDS: Complete layout for the IP, with a verified layer map to ensure proper import into the SoC database. The GDS is uniquified to prevent name clashes at the SoC level, and is used to confirm LVS and DRC results at the block